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| IN74ACT533 OCTAL 3-STATE INVERTING TRANSPARENT LATCH High-Speed Silicon-Gate CMOS The IN74ACT533 is identical in pinout to the LS/ALS533, HC/HCT533. The IN74ACT533 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. The data appears as the outputs in inverted form. When Latch Enable goes low, data meeting the setup and hold time becomes latched. The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high-impedance state. Thus, data may be latched even when the outputs are not enabled. * TTL/NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 A; 0.1 A @ 25C Outputs Source/Sink 24 mA 3-State Outputs for Bus Interfacing LOGIC DIAGRAM * * * * * ORDERING INFORMATION IN74ACT533N Plastic IN74ACT533DW SOIC TA = -40 to 85 C for all packages PIN ASSIGNMENT FUNCTION TABLE Output Enable L L L H Inputs Latch Enable H H L X D H L X X Output Q L H no chang e Z PIN 20=VCC PIN 10 = GND X = don't care Z = high impedance 1 IN74ACT533 MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin mA 20 IOUT DC Output Sink/Source Current, per Pin mA 50 ICC DC Supply Current, VCC and GND Pins mA 50 PD Power Dissipation in Still Air, Plastic DIP+ 750 mW SOIC Package+ 500 Tstg Storage Temperature -65 to +150 C 260 TL Lead Temperature, 1 mm from Case for 10 C Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TJ Junction Temperature (PDIP) TA Operating Temperature, All Package Types IOH Output Current - High IOL Output Current - Low t r, tf Input Rise and Fall Time * VCC =4.5 V VCC =5.5 V (except Schmitt Inputs) * VIN from 0.8 V to 2.0 V Min 4.5 0 Max 5.5 VCC 140 +85 -24 24 10 8.0 Unit V V C C mA mA ns/V -40 0 0 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 IN74ACT533 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Guaranteed VCC Limits Symbol Parameter Test Conditions V 25 C -40C to 85C VOUT= 0.1 V or VCC-0.1 VIH Minimum High4.5 2.0 2.0 Level Input V 5.5 2.0 2.0 Voltage VOUT= 0.1 V or VCC-0.1 VIL Maximum Low 4.5 0.8 0.8 Level Input V 5.5 0.8 0.8 Voltage VOH Minimum High4.5 4.4 4.4 IOUT -50 A Level Output 5.5 5.4 5.4 Voltage * VIN=VIH or VIL 3.76 3.86 4.5 IOH=-24 mA 4.76 4.86 5.5 IOH=-24 mA VOL Maximum Low4.5 0.1 0.1 IOUT 50 A Level Output 5.5 0.1 0.1 Voltage * VIN= VIH or VIL 0.44 0.36 4.5 IOL=24 mA 0.44 0.36 5.5 IOL=24 mA IIN Maximum Input VIN=VCC or GND 5.5 0.1 1.0 Leakage Current 5.5 1.5 Additional Max. VIN=VCC - 2.1 V ICCT ICC/Input 5.5 IOZ Maximum Three- VIN (OE)= VIH or VIL 0.5 5.0 State Leakage VIN =VCC or GND Current VOUT =VCC or GND VOLD=1.65 V Max IOLD +Minimum 5.5 75 Dynamic Output Current VOHD=3.85 V Min IOHD +Minimum 5.5 -75 Dynamic Output Current VIN=VCC or GND ICC Maximum 5.5 8.0 80 Quiescent Supply Current (per Package) * All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2.0 ms, one output loaded at a time. Unit V V V V A mA A mA mA A 3 IN74ACT533 AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V 10%, CL=50pF,Input tr=tf=3.0 ns) Guaranteed Limits Unit Symbol Parameter 25 C -40C to 85C Min Max Min Max tPLH Propagation Delay, Input D to Q (Figure 1) 2.5 10.5 2.0 11.5 ns tPHL Propagation Delay, Input D to Q (Figure 1) 2.5 10.0 2.0 11.0 ns tPLH Propagation Delay, Latch Enable to Q 2.5 10.5 2.0 11.5 ns (Figure 2) tPHL Propagation Delay, Latch Enable to Q 2.5 10.5 2.0 11.5 ns (Figure 2) tPZH Propagation Delay, Output Enable to Q 2.0 10.0 1.5 11.0 ns (Figure 3) tPZL Propagation Delay, Output Enable to Q 2.0 10.0 1.5 11.0 ns (Figure 3) tPHZ Propagation Delay, Output Enable to Q 2.0 10.0 1.5 11.0 ns (Figure 3) tPLZ Propagation Delay, Output Enable to Q 2.0 10.0 1.5 11.0 ns (Figure 3) CIN Maximum Input Capacitance 4.5 4.5 pF Typical @25C,VCC=5.0 V 40 CPD Power Dissipation Capacitance pF TIMING REQUIREMENTS(VCC=5.0 V 10%, CL=50pF, Input tr=tf=3.0 ns) Guaranteed Limits Symbol Parameter 25 C -40C to 85C tsu Minimum Setup Time, Input D to Latch 3.0 4.0 Enable (Figure 4) th Minimum Hold Time, Latch Enable to 2.0 2.5 Input D (Figure 4) tw Minimum Pulse Width, Latch Enable 5.0 6.0 (Figure 2) Unit ns ns ns 4 IN74ACT533 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms EXPANDED LOGIC DIAGRAM 5 |
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